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Hierarchy
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Hierarchy for test
test
simplecore
busCtl
control
aluDebug
decode
execute
fetch
instDebug
datapath
alu
dAreg
dOutreg
iAreg
incr
mul
regFile
gpr
x 15
regSel
x 2
shifter
sr
sram1k16
x 2
Hierarchy
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This page:
Created:
Wed Sep 5 13:28:33 2001
Verilog converted to html by
v2html 6.0
(written by
Costas Calamvokis
).
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