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1998 Library Development Environment
Portfolio(Eng.) |
2008/05/08 21:08
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Based on the technology developed IDEC Library, a formal environment was developed for over 400 cells on 0.25um CMOS technology.
It generates Synopsys Synthesis Library and Verilog Simulation Library from a common functional description and automatically characterize the timing information by generating HSPICE routines.
I designed two test vehicle for evaluation. One of them was fabricated for function test and the other for timing characteristics test.
2008/05/08 21:08 Donny  |
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 Standard Cell Library |
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| Trackback http://www.donny.co.kr/tt/trackback/37 |
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| Chip Designer, Donny
(drdonny@gmail.com) |
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Innovate or Die
2011/10
