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Microprocessor 에 해당하는 글10 개

2008/05/08 CICC 2004 - Single-Chip Programmable Processor Array

2008/05/08 ISSCC 2003 - RamP-IV

2008/05/08 ISSCC 2002 - Single-Chip Programmable Platform

2008/05/08 ISSCC 2002 Press Release

2008/05/08 2001 Multithreded ARM Processor

2008/05/08 2000 Press Release on Low Power Embedded Processor (TJ News)

2008/05/08 2000 Press Release on Low Power Embedded Processor (ET News)

2008/05/08 2000 Low Power Embbedded Processor (TV News)

2008/05/08 2000 ARMISS (ARM Instruction Simulator)

2008/05/08 1999 ARM7 Compatible Processor

CICC 2004 - Single-Chip Programmable Processor Array
Portfolio(Eng.) | 2008/05/08 22:28

In the year 2004, I presented the paper entitled "A 4.75GOPS single-chip programmable processor array consisting of a multithreaded processor and multiple SIMD and IO processors" at IEEE CICC (Custom Integrated Circuit Conference) in 2004.

CICC is the second biggest conference after ISSCC (International Solid-State Circuit Conference) for the chip designers.

Now the dual-core and quad-core is available at the market. Integrating nine processors including a multi-threaded processor on a single die is very aggressive challenge at that time.

The aim of the chip is implementing a system chip just by software programming.
The IO processors are dedicated to process concurrent IO behavior. SIMD(Single Instruction Multiple Data) processors process the media (video or audio) applications in parallel and multhreaded processor processes concuffent system behavior with fast context switching.

Die Photo of Single-Chip Programmable Processor Array

CICC, Microprocessor

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ISSCC 2003 - RamP-IV
Portfolio(Eng.) | 2008/05/08 22:28

In the year 2003, I and SSL team presented "A 210mW Graphics LSI implementing Full 3D Pipeline with 264Mtexels/s Texturing for Mobile Multimedia Applications" at ISSCC (International Solid-State Circuit Conference)

I designed the 5-stage RISC processor with 8KB Instruction and Data Cache for 3D geomery processing and founded the full-chip integration flow with automatic P&R with Apollo (now it is Astro).

Die Photo of RamP-IV

Microscopic signature on the chip.

RamP-IV is the world first all-in-one 3D graphic processor for mobiel application and successfully demonstrated displaying on VGA display on the prototype system.

Ramp-IV Evaluation Environment

Ramp-IV Evaluation Environment (Revised)

ISSCC, Microprocessor

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ISSCC 2002 - Single-Chip Programmable Platform
Portfolio(Eng.) | 2008/05/08 22:26

In the year 2002, I presented the paper about the multithreaded processor incorporating configurable logics at ISSCC (International Solid-State Circuit Conference).
Until then multithreading was just one of the concepts in the papers or textbooks. I adapted the multithreading concept to ARM processor to enhance concurrent control for complex behavior for system chip and configurable logics for implement dedicated hardwares.

The block names as CLC (Configurable Logic Cluster) is a type of FPGA (Field Programmable Gate Array) for ASIC foundry. I designed the architecture for programmable logic including routings and look-up tables, drew the layout and ported it to P&R software by myself.

Die Photo of Single-Chip Programmable Platform

It was the great honor for me as it is the first paper presented in the microprocessor session in ISSCC for my mother country. It is very obvious how it is hard to present a paper for its microprocessor session if you have a look on the program book below as all the papers came from industry top companies including Compaq, Sun, IBM, Intel, Hewlett Packard.

The picture above was taken after the rehearsal at the day before the conference with the chairman, co-chairman and other speekers for the same session. The co-chairman was Simon Segars, Executive Vice President of ARM Ltd. As I was involved in the ARM compatible processor development project for years, I read his articles many times and my design is also based on ARM architecture. So it was very nice to see him and very challenging to rehearse in fromt of him.

ISSCC.ARM, Microprocessor

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ISSCC 2002 Press Release
Portfolio(Eng.) | 2008/05/08 22:26

Multithreaing was one of the hottest issues at the ISSCC 2002 as two papers in the microprocessor session newly employed multithreading at the same time.
As it was a year before Intel announced to introduce Hyper-Threading, multithreading was brand-new technology for industries at that time.
As the impact of ISSCC is very huge, they didn't hesitate to say Multi-threading "rules".

ISSCC, Microprocessor, multithreading, Press Release

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2001 Multithreded ARM Processor
Portfolio(Eng.) | 2008/05/08 22:25

This is the prototype of Multithreded ARM Processor with 4-Kbytes Embeede SRAM.
Before integrating to Single-Chip Programmable Platform, it was evaluated as a separated chip. It can store four context with the individual register file and switch among the context very fast.

Layout of the Multithreaded ARM Processor

Microprocessor, multithreading

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2000 Press Release on Low Power Embedded Processor (TJ News)
Portfolio(Eng.) | 2008/05/08 22:24

2000.7.10

Microprocessor, Press Release

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2000 Press Release on Low Power Embedded Processor (ET News)
Portfolio(Eng.) | 2008/05/08 22:22

2000.7.6.

Microprocessor, Press Release

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2000 Low Power Embbedded Processor (TV News)
Portfolio(Eng.) | 2008/05/08 22:22

2000.7.7.

Microprocessor, Press Release

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2000 ARMISS (ARM Instruction Simulator)
Portfolio(Eng.) | 2008/05/08 22:21

ARMISS (ARM Instruction Set Simulator) is developed for ARM7/ARM9 Compatible Processor Design.
ARMISS can run the binary image file from ARM compiler for compatibility test.
ARMISS is a cycle-accurate simulator to validate accurate pipelined operation and it also can be compiled to BFM (Bus Functional Model) for a System-on-Chip design.
It saves simulation time as it is hundred times the faster than Verilog RTL Simulation.

SoftARM is Graphic User Interface based on GTK+ (The GIMP Toolkit) which is connected to ARMISS through ARMISS via IPC (Inter-Process Communication). SoftARM also can be connected to Verilog Simulator via IPC to control and monitor the simulation.

ARM, ISS, Microprocessor

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1999 ARM7 Compatible Processor
Portfolio(Eng.) | 2008/05/08 22:19

In 1999, I leaded a project to develop the embedded processor design technology with the sponsorship of Korea Ministry of Science and Technology, Korea Ministry of Commerce, Industry and Energy.
In order to catch up the state-of-art technology, I designed the ARM7TDMI compatible processor first.
The behavioral compatibility is verified by developing the instruction set simulator, ARMISS and
prototyping with FPGA.

It was integrated to RamP processor which using the MML (Merged Memory Logic) process.
As the MML process is not developed for the commercial usage, there was no standard cell library. I developed not only the processor but also the standard cell library for it with the technology that I developed for IDEC library.